A Power-Efficient Successive Approximation ADC Using an Improved Control Logic Circuit

A Power-Efficient Successive Approximation ADC Using an Improved Control Logic Circuit

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Publishing year : 2012

Conference : 20th Iranian Conference on Electrical Engineering

Number of pages : 4

Abstract: In this paper, a new control logic circuit for a successive approximation register is proposed for analog-to-digital converter (SA-ADC). In the proposed digital circuit architecture, the number of flip-flops is reduced and flip-flops do not need set and reset nodes. The simulation results of a 5-bit, 100 MS / s ADC and 0.18-m technology show that the digital power consumption of the proposed structure is reduced by a factor of 17%, and the total power consumption is reduced by about 10% in comparison with the Conventional counterpart.