Part of #Fully Digital ADCs Using Delay Element# :
Publishing year : 2008
Conference : Sixteenth Iranian Conference on Electrical Engineering
Number of pages : 5
Abstract: Fully digital analog to digital converters (FD-ADC) have potential applications in very low power ICs and can be implemented in digital CMOS technology. In this paper, a full digital ADC, using a new current starved delay element, is presented. The linearity of the delay element is discussed and its impact on the overall performance of the ADC is addressed. It is shown that increasing the linearity of the delay element can increase the FD-ADC signal to noise plus deformation ratio (SNDR).