Pipeline Architecture for Reed-Solomon Codec

Pipeline Architecture for Reed-Solomon Codec

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Part of #Pipeline Architecture for Reed-Solomon Codec# :

Publishing year : 2005

Conference : Thirteenth Iranian Conference on Electrical Engineering

Number of pages : 6

Abstract: Reliability and data rates are two basic factors in QoS in mobile communications networks. This can be achieved by adding redundancy bits (i.e. error detection and correction codes) to refer to reliability. Reed-Solomon coding is one of the most important schemes for this purpose to achieve error correction. In this paper, a solution for a RS-decoder is proposed to reduce processing time. In the pipeline architecture the number of steps to perform is in three stages, so the ideal speed up must become1.8. Because of the data dependency between the stages, the achieved speed up is 1 & lt; S & gt; 1.8. The hardware description language (HDL) method is used to hardware synthesis the Reed-Solomon encoder and decoder on FPGA devices.